Embodiments of the present invention relate to a non-volatile memory device and a method for forming the same, and more specifically, to a ferroelectric memory device having non-volatile characteristics.
Generally, a non-volatile ferroelectric memory (e.g., a Ferroelectric Random Access Memory (FeRAM)) has a data processing speed similar to that of a Dynamic Random Access Memory (DRAM). A non-volatile ferroelectric memory also preserves data even when power is turned off. Because of these properties, many developers are conducting intensive research into FeRAM as a next generation memory device.
The above-mentioned FeRAM has a very similar structure to that of DRAM, and uses a ferroelectric capacitor as a memory device. Ferroelectric substances have high residual polarization characteristics, such that data is not deleted although an electric field is removed.
A conventional 1-Transistor 1-Capacitor (1T1C)-type unit cell includes one switching element, which performs a switching operation according to a word line state and couples a bit line to a non-volatile ferroelectric capacitor, and one non-volatile ferroelectric capacitor coupled between one end of the switching element and a plate line.
The switching element of the conventional non-volatile ferroelectric memory device is generally formed of an N-type Metal Oxide Semiconductor (NMOS) transistor switched by a gate control signal.
FIG. 1 is a cross-sectional view illustrating a cell used in a conventional semiconductor memory device.
Referring to FIG. 1 a conventional semiconductor memory device includes an one-transistor Field Effect Transistor (1-T FET)-type ferroelectric memory cell.
A memory cell of the related art includes a P-type channel region formed over a P-type semiconductor substrate 1, an N-type drain region 2 and an N-type source region 3. A ferroelectric layer 4 is formed over a channel region, and a word line 5 is formed over the ferroelectric layer 4.
A buffer insulation layer 6 may be formed between the channel region and the ferroelectric layer 4 for fabrication stabilization. That is, the buffer insulation layer 6 may be formed to overcome problems that result from a difference in an electrical property between the channel region and the ferroelectric layer 4.
The above-mentioned semiconductor memory device is configured to read/write data using memory-cell channel resistance characteristics that change according to the polarization state of the ferroelectric layer 4.
In other words, if the polarity of the ferroelectric layer 4 induces a positive (+) charge in a channel, the memory cell is at a high-resistance channel state so that the memory cell is turned off. In contrast, if the polarity of the ferroelectric layer 4 induces a negative (−) charge in the channel, the memory cell is at a low-resistance channel state so that the memory cell is turned on. In this way, the conventional ferroelectric memory cell selects the polarization type of the ferroelectric layer 4 and writes or reads data in a cell, so that it can serve as a non-volatile memory cell.
However, while the memory cell of the conventional 1T-FET-type ferroelectric memory device has non-volatile characteristics, cell data deteriorates with a lapse of time so that the data retention lifetime is limited. As a result, it is difficult to keep data using non-volatile cell storage characteristics for a long period of time.
In addition, the conventional ferroelectric memory device controls a current using a lower semiconductor substrate. The lower P-type substrate 1 may be formed of silicon (Si), germanium (Ge), or the like. A metal-based ferroelectric layer 4 and the semiconductor substrate have different electrical characteristics. Thus, an interface between the ferroelectric layers 4 and the semiconductor substrate may deteriorate rapidly with a lapse of time, so that it is hard to guarantee stable operation.